AC-Transformer-RHB: Logic + ReRAM 3D Chip

Technology Edges and Chip Highlights

By adopting CMOS and ReRAM integrated processes, using AI computing chip stacked with ReRAM memory and architectural innovations, effectively reduced both system power consumption and system cost for large model deployment
Leveraging software-hardware co-design technologies tailored for 3D logic-ReRAM stacking in large model architectures—such as near-memory processing, low-bit quantization, and speculative decoding—achieves an external memory access compression rate of 75–80%
From 2D to 3D, the global interconnect length of high-density AI computing cores is reduced by more than 50%, while 3D wiring shortens the connection length between ReRAM and compute units by 85%
Based on co-design methodology and self-developed toolchains, efficient memory management, dataflow scheduling, and instruction parallelism are achieved on multi-core architectures