Publications

Sections
Text Area
[103] Y. Lu, S. Liu, Q. Zhang, and Z. Xie, “RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model,” in 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
[102] X. Wang, F. Tian, X. Chen, et al., A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications, 2023.
[101] Z. Rong, L. Zhang, and M. Chan, “Generic Memory Modeling with Recurrent Neural Network,” in 2022 10th International Symposium on Next-Generation Electronics (ISNE), 2023, pp. 1–3.
[100] Z. Xie, T. Zhang, and Y. Peng, “Security and Reliability Challenges in Machine Learning for EDA: Latest Advances,” in 2023 24th International Symposium on Quality Electronic Design (ISQED), 2023, pp. 1–6.
[99] J. He, Y. Huang, M. Lastras, T. T. Ye, C.-Y. Tsui, and K.-T. Cheng, “RVComp: Analog Variation Compensation for RRAM-based In-Memory Computing,” in 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 2023, pp. 1–6.
[98] T. Liu and E. F. Young, “Rethinking AIG Resynthesis in Parallel,” in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1–6.
[97] R. Mao, X. Sheng, C. Graves, C. Xu, and C. Li, “ReRAM-based graph attention network with node-centric edge searching and hamming similarity,” in 2023 60th ACM/IEEE Design Automation Confer- ence (DAC), 2023, pp. 1–6.
[96] A. Ahmad, Z. Xie, and W. Zhang, “PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search,” in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1–6.
[95] X. Chen, R. Pan, X. Wang, F. Tian, and C.-Y. Tsui, “Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification,” in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1–2.
[94] L. Liu, S. Kumar, S. Thomann, H. Amrouch, and X. S. Hu, “Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs,” in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1–6.
[93] J. Chen, F. Tu, K. Shao, et al., “AutoDCIM: An Automated Digital CIM Compiler,” in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1–6.
[92] H. Yuan, Y. Char, S. Dai, et al., “Design and demonstration of Cu/Al2O3 /Cu RRAM with complementary resistance switching characteristic,” in 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2023, pp. 1–3.
[91] S.-Q. Dai, C. J. Estrada, A. Xiong, et al., “A Multiple Junction Photonic Demodulator with Low Power Consumption for Time-of-Flight Application,” in 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2023, pp. 1–3.
[90] T. Srimani, R. M. Radway, J. Kim, et al., “Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits,” in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, pp. 1–6.
[89] L. Chen, X. Li, F. Jiang, C. Li, and J. Xu, “Smart Knowledge Transfer-based Runtime Power Management,” in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, pp. 1–6.
[88] Y. Zhang, S. R. Sathi, Z. Kou, S. Sinha, and W. Zhang, “Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform,” in 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 174–183.
[87] J. Wu, J. Zhou, Y. Gao, Y. Ding, N. Wong, and H. K.-H. So, “MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources,” in 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 94–104.
[86] Y. Ding, J. Wu, Y. Gao, M. Wang, and H. K.-H. So, “Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming,” in 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 83–93.
[85] H. Wang, Y. Qin, C. Lao, Y. Le, W. Wu, and K. Chen, “Preemptive Switch Memory Usage to Accelerate Training Jobs with Shared In-Network Aggregation,” in 2023 IEEE 31st International Conference on Network Protocols (ICNP), 2023.
[84] Z. Yan, Y. Qin, X. S. Hu, and Y. Shi, “On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators,” in 2023 IEEE 36th International System-on-Chip Conference (SOCC), 2023, pp. 1–6.
[83] J. He, Z. Shen, F. Tian, et al., “SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks,” in 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023, pp. 1–5.
[82] F. Tian, X. Wang, J. Chen, et al., “Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System,” in 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023, pp. 1–5.
[81] S. Jiang, T.-W. Huang, and T.-Y. Ho, “GLARE: Accelerating Sparse DNN Inference Kernels with Global Memory Access Reduction,” in 2023 IEEE High Performance Extreme Computing Conference (HPEC), 2023.
[80] K. T. Phan, Y. Gao, and H. C. Luong, “A 10.8-14.5GHz 8-Phase 12.5%-Duty-Cycle Non-Overlapping LO Generator with Automatic Phase-and-Duty-Cycle Calibration for 60-GHz 8-Path-Filtering Sub- Sampling Receivers,” in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023, pp. 205–208.
[79] K. Toprasertpong, S. Liu, J. Chen, et al., “Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, pp. 1–2.
[78] A. Wei, A. Levy, P. Yi, et al., “PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.
[77] Q. Zhang, S. Li, G. Zhou, et al., “PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.
[76] W. Fang, Y. Lu, S. Liu, et al., “MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.
[75] S. Zheng, L. Zou, P. XU, S. Liu, B. Yu, and M. Wong, “Lay-Net: Grafting Netlist Knowledge on Layout- Based Congestion Prediction,” in 2023 IEEE/ACM International Conference On Computer Aided De- sign (ICCAD), 2023.
[74] C. BAI, X. Wei, Y. Zhuo, et al., “Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.
[73] Z. Yan, Y. Qin, W. Wen, X. S. Hu, and Y. Shi, “Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.
[72] A. F. Laguna, M. M. Sharifi, D. Reis, et al., “Algorithm/Hardware Co-design for Few-Shot Learning at the Edge,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Invited paper, 2023.
[71] J. Jiang, X. Chen, and C.-Y. Tsui, “Accelerating Large Kernel Convolutions with Nested Winograd Transformation,” in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC), 2023.
[70] G. A. Eggermann, M. A. Rios, G. Ansaloni, and D. Atienza Alonso, “A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication,” in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC), 2023, p. 6.
[69] S. Liu, K. Jana, K. Toprasertpong, et al., “Gain Cell Memory on Logic Platform - Device Guidelines for Oxide Semiconductor Transistor Materials Development,” in 2023 International Electron Devices Meeting (IEDM), 2023.
[68] S. Zheng, H. Geng, C. Bai, B. Yu, and M. D. F. Wong, “Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-Objective Trust-Region Bayesian Optimization,” ACM Trans. Des. Autom. Electron. Syst., vol. 28, no. 5, Sep. 2023.
[67] F. Ponzina, M. Rios, A. Levisse, G. Ansaloni, and D. Atienza, “Overflow-Free Compute Memories for Edge AI Acceleration,” ACM Trans. Embed. Comput. Syst., vol. 22, no. 5s, Sep. 2023.
[66] B. Shao, T. Wan, F. Liao, et al., “Highly Trustworthy In-Sensor Cryptography for Image Encryption and Authentication,” ACS Nano, vol. 17, no. 11, pp. 10 291–10 299, 2023.
[65] L. R. Upton, A. Levy, M. D. Scott, et al., “EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry,” in ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, pp. 469–472.
[64] F. Tian, X. Wang, J. Chen, et al., “BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare,” in ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, pp. 225–228.
[63] X. Hou, J. Liu, X. Tang, et al., “MMExit: Enabling Fast and Efficient Multi-modal DNN Inference with Adaptive Network Exits,” in Euro-Par 2023: Parallel Processing, Cham: Springer Nature Switzerland, 2023, pp. 426–440.
[62] C. Tao, L. Hou, H. Bai, et al., “Structured Pruning for Efficient Generative Pre-trained Language Models,” in Findings of the Association for Computational Linguistics: ACL 2023, Toronto, Canada: Association for Computational Linguistics, Jul. 2023, pp. 10 880–10 895.
[61] B. Bartan and M. Pilanci, “Randomized Polar Codes for Anytime Distributed Machine Learning,” IEEE Journal on Selected Areas in Information Theory, vol. 4, pp. 393–404, 2023.
[60] L. Liu, A. F. Laguna, R. Rajaei, et al., “A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 6, pp. 2356–2369, 2023.
[59] X. Hu, X. Liu, Y. Liu, et al., “A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 8, pp. 3079–3083, 2023.
[58] P. Zhang, Z. Ge, L. Song, and E. Y. Lam, “Neuromorphic Imaging With Density-Based Spatiotemporal Denoising,” IEEE Transactions on Computational Imaging, vol. 9, pp. 530–541, 2023.
[57] X. Chen, J. Zhu, J. Jiang, and C.-Y. Tsui, “Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 42, no. 2, pp. 644–657, 2023.
[56] H. Geng, T. Chen, Y. Ma, B. Zhu, and B. Yu, “PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 1, pp. 178–189, 2023.
[55] R. Zhang, C. Tang, X. Sun, et al., “Sky-TCAM: Low-Power Skyrmion-Based Ternary Content Addressable Memory,” IEEE Transactions on Electron Devices, vol. 70, no. 7, pp. 3517–3522, 2023.
[54] S. Zhang, N. Meng, and E. Y. Lam, “LRT: An Efficient Low-Light Restoration Transformer for Dark Light Field Images,” IEEE Transactions on Image Processing, vol. 32, pp. 4314–4326, 2023.
[53] S. Wang, Y. Li, D. Wang, et al., “Echo state graph neural networks with analogue random resistive memory arrays,” Nature Machine Intelligence, vol. 5, no. 2, pp. 104–113, Feb. 2023.
[52] Z. Ge, H. Wei, F. Xu, et al., “Millisecond autofocusing microscopy using neuromorphic event sensing,” Optics and Lasers in Engineering, vol. 160, p. 107 247, 2023.
[51] P. Yi and S. Achour, “Hardware-Aware Static Optimization of Hyperdimensional Computations,” Proc. ACM Program. Lang., vol. 7, no. OOPSLA2, Oct. 2023.
[50] Z. Xie, “Efficient Runtime Power Modeling with On-Chip Power Meters,” in Proceedings of the 2023 International Symposium on Physical Design, ser. ISPD ’23, Virtual Event, USA: Association for Computing Machinery, 2023, pp. 168–174.
[49] C.-C. Chang, J. Pan, Z. Xie, J. Hu, and Y. Chen, “Rethink before Releasing Your Model: ML Model Extraction Attack in EDA,” in Proceedings of the 28th Asia and South Pacific Design Automation Conference, ser. ASPDAC ’23, Tokyo, Japan: Association for Computing Machinery, 2023, pp. 252–257.
[48] C.-C. Chang, J. Pan, Z. Xie, et al., “Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction,” in Proceedings of the 28th Asia and South Pacific Design Automation Conference, ser. ASPDAC’23, Tokyo, Japan: Association for Computing Machinery, 2023, pp. 58–63.
[47] F. Zhang and M. Pilanci, “Optimal Shrinkage for Distributed Second-Order Optimization,” in Proceedings of the 40th International Conference on Machine Learning, ser. Proceedings of Machine Learning Research, vol. 202, PMLR, Jul. 2023, pp. 41 523–41 549.
[46] A. Mishkin and M. Pilanci, “Optimal Sets and Solution Paths of ReLU Networks,” in Proceedings of the 40th International Conference on Machine Learning, ser. Proceedings of Machine Learning Research, vol. 202, PMLR, Jul. 2023, pp. 24 888–24 924.
[45] M. Wang, I. McInerney, B. Stellato, S. Boyd, and H. K.-H. So, “RSQP: Problem-Specific Architectural Customization for Accelerated Convex Quadratic Optimization,” in Proceedings of the 50th Annual International Symposium on Computer Architecture, ser. ISCA ’23, Orlando, FL, USA: Association for Computing Machinery, 2023.
[44] X. Hou, J. Liu, X. Tang, et al., “Architecting Efficient Multi-Modal AIoT Systems,” in Proceedings of the 50th Annual International Symposium on Computer Architecture, ser. ISCA ’23, Orlando, FL, USA: Association for Computing Machinery, 2023.
[43] S. Jiang, T.-W. Huang, B. Yu, and T.-Y. Ho, “SNICIT: Accelerating Sparse Neural Network Inference via Compression at Inference Time on GPU,” in Proceedings of the 52nd International Conference on Parallel Processing, ser. ICPP ’23, Salt Lake City, UT, USA: Association for Computing Machinery, 2023, pp. 51–61.
[42] T. Ergen, H. I. Gulluk, J. Lacotte, and M. Pilanci, “Globally Optimal Training of Neural Networks with Threshold Activation Functions,” in The Eleventh International Conference on Learning Representations, 2023.
[41] Y. Wang and M. Pilanci, “Sketching the Krylov subspace: faster computation of the entire ridge regularization path,” The Journal of Supercomputing, vol. 79, no. 16, pp. 18 748–18 776, May 2023.
[40] C. Tao and N. Wong, “ODG-Q: Robust Quantization via Online Domain Generalization,” in 2022 26th International Conference on Pattern Recognition (ICPR), 2022, pp. 1822–1828.
[39] L. Chen, X. Li, and J. Xu, “Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement Learning,” in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, pp. 1371–1376.
[38] Y. Liu, J. Zhang, J. Feng, S. Chen, and J. Xu, “A Reliability Concern on Photonic Neural Networks,” in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, pp. 1059–1064.
[37] Z. Guan, W. Zhou, Y. Ren, R. Xie, H. Yu, and N. Wong, “A Hardware-Aware Neural Architecture Search Pareto Front Exploration for In-Memory Computing,” in 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022, pp. 1–4.
[36] A.-N. Xiong, Y.-F. Fan, S.-Q. Dai, C. Xu, J. G. Yuan, and M. Chan, “A CMOS Compatible In-sensor Computing Neural Network with Gate/Body-Tied PMOSFET Array,” in 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022, pp. 1–3.
[35] X. Wang, X. Liu, X. Hu, et al., “TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network,” in 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, pp. 66–69.
[34] X. Li, L. Chen, S. Chen, F. Jiang, C. Li, and J. Xu, “Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning,” in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, pp. 164–169.
[33] J. Feng, S. Chen, J. Zhang, Y. Fu, and J. Xu, “Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems,” in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, pp. 122–127.
[32] R. Wang and W.-N. Lee, “A General Deep Learning Model for Ultrasound Localization Microscopy,” in 2022 IEEE International Ultrasonics Symposium (IUS), 2022, pp. 1–4.
[31] S. Lin and M. D. Wong, “Superfast Full-Scale GPU-Accelerated Global Routing,” in 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, pp. 1–8.
[30] C. Li, F. Jiang, S. Chen, et al., “Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet,” in 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, pp. 1–9.
[29] Z. Liu, K.-T. Cheng, D. Huang, E. Xing, and Z. Shen, “Nonuniform-to-Uniform Quantization: Towards Accurate Quantization via Generalized Straight-Through Estimation,” in 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), Los Alamitos, CA, USA: IEEE Computer Society, Jun. 2022, pp. 4932–4942.
[28] Z. Xiao, V. B. Naik, S. K. Cheung, et al., “Device Variation-Aware Adaptive Quantization for MRAM- based Accurate In-Memory Computing Without On-chip Training,” in 2022 International Electron Devices Meeting (IEDM), 2022, pp. 10.5.1–10.5.4.
[27] M. Jiang, K. Shan, X. Sheng, C. Graves, J. P. Strachan, and C. Li, “An efficient synchronous-updating memristor-based Ising solver for combinatorial optimization,” in 2022 International Electron Devices Meeting (IEDM), 2022, pp. 22.2.1–22.2.4.
[26] Y. Li, W. Zhang, X. Xu, et al., “Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory,” Advanced Intelligent Systems, vol. 4, no. 8, p. 2 200 026, 2022.
[25] S. Wang, H. Chen, W. Zhang, et al., “Convolutional Echo-State Network with Random Memristors for Spatiotemporal Signal Classification,” Advanced Intelligent Systems, vol. 4, no. 8, p. 2 200 027, 2022.
[24] X. Hou, C. Xu, J. Liu, et al., “Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs,” IEEE Computer Architecture Letters, vol. 21, no. 2, pp. 125–128, 2022.
[23] M. Schaller, G. Banjac, S. Diamond, A. Agrawal, B. Stellato, and S. Boyd, “Embedded Code Generation With CVXPY,” IEEE Control Systems Letters, vol. 6, pp. 2653–2658, 2022.
[22] R. Mao, B. Wen, M. Jiang, J. Chen, and C. Li, “Experimentally-Validated Crossbar Model for Defect- Aware Training of Neural Networks,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 5, pp. 2468–2472, 2022.
[21] H. Geng, Y. Ma, Q. Xu, J. Miao, S. Roy, and B. Yu, “High-Speed Adder Design Space Exploration via Graph Neural Processes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 8, pp. 2657–2670, 2022.
[20] J. Zheng, Y. Liu, X. Liu, L. Liang, D. Chen, and K.-T. Cheng, “ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor With Compiler-Architecture Co-Design,” IEEE Transactions on Computers, vol. 71, no. 12, pp. 3088–3100, 2022.
[19] S.-Q. Dai, C. J. Estrada, A.-N. Xiong, C. Xu, J. G. Yuan, and M. Chan, “A CMOS-Compatible Photonic Demodulator With Low-Power Consumption for Time-of-Flight Image Sensor,” IEEE Transactions on Electron Devices, vol. 69, no. 11, pp. 6178–6183, 2022.
[18] C. Tao, R. Lin, Q. Chen, Z. Zhang, P. Luo, and N. Wong, “FAT: Frequency-Aware Transformation for Bridging Full-Precision and Low-Precision Deep Representations,” IEEE Transactions on Neural Networks and Learning Systems, pp. 1–15, 2022.
[17] M. Wang, S. Rasoulinezhad, P. H. W. Leong, and H. K.-H. So, “NITI: Training Integer Neural Networks Using Integer-Only Arithmetic,” IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 11, pp. 3249–3261, 2022.
[16] X. Chen, Y. Fu, J. Feng, J. Zhang, S. Chen, and J. Xu, “Improving the thermal reliability of photonic chiplets on multicore processors,” Integration, vol. 86, pp. 9–21, 2022.
[15] Y. Zhang, Y. Deng, Y. Lin, et al., “Oscillator-Network-Based Ising Machine,” Micromachines, vol. 13, no. 7, 2022.
[14] R. Mao, B. Wen, A. Kazemi, et al., “Experimentally validated memristive memory augmented neural network with efficient hashing and similarity search,” Nature Communications, vol. 13, no. 1, Oct. 2022.
[13] Z. Jiang, W. Wang, B. Li, and B. Li, “Pisces: Efficient Federated Learning via Guided Asynchronous Training,” in Proceedings of the 13th Symposium on Cloud Computing, ser. SoCC ’22, San Francisco, California: Association for Computing Machinery, 2022, pp. 370–385.
[12] Y. Gao, S. Wang, and H. K.-H. So, “REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs,” in Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ’22, Virtual Event, USA: As- sociation for Computing Machinery, 2022, pp. 158–168.
[11] X. Huang, Z. Shen, S. Li, et al., “SDQ: Stochastic Differentiable Quantization with Mixed Precision,” in Proceedings of the 39th International Conference on Machine Learning, ser. Proceedings of Machine Learning Research, vol. 162, PMLR, Jul. 2022, pp. 9295–9309.
[10] B. Bartan and M. Pilanci, “Neural Fisher Discriminant Analysis: Optimal Neural Network Embeddings in Polynomial Time,” in Proceedings of the 39th International Conference on Machine Learning, ser. Proceedings of Machine Learning Research, vol. 162, PMLR, Jul. 2022, pp. 1647–1663.
[9] L. Liu, B. Fu, M. D. F. Wong, and E. F. Y. Young, “Xplace: An Extremely Fast and Extensible Global Placement Framework,” in Proceedings of the 59th ACM/IEEE Design Automation Conference, ser. DAC ’22, San Francisco, California: Association for Computing Machinery, 2022, pp. 1309–1314.
[8] H. Geng, Q. Xu, T.-Y. Ho, and B. Yu, “PPATuner: Pareto-Driven Tool Parameter Auto-Tuning in Physical Design via Gaussian Process Transfer Learning,” in Proceedings of the 59th ACM/IEEE Design Automation Conference, ser. DAC ’22, San Francisco, California: Association for Computing Machinery, 2022, pp. 1237–1242.
[7] S. Lin, J. Liu, T. Liu, M. D. F. Wong, and E. F. Y. Young, “NovelRewrite: Node-Level Parallel AIG Rewriting,” in Proceedings of the 59th ACM/IEEE Design Automation Conference, ser. DAC ’22, San Francisco, California: Association for Computing Machinery, 2022, pp. 427–432.
[6] C. Tao, L. Hou, W. Zhang, et al., “Compression of Generative Pre-trained Language Models via Quantization,” in Proceedings of the 60th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), Dublin, Ireland: Association for Computational Linguistics, May 2022, pp. 4821–4836.
[5] Q. Lu and B. Murmann, “Improving the Energy Efficiency and Robustness of tinyML Computer Vision using Log-Gradient Input Images,” in Proceedings of tinyML Research Symposium (tinyML Research Symposium’22), ACM, 2022.
[4] S.-Q. Dai, C. J. Estrada, A.-N. Xiong, C. Xu, G. J. Yuan, and M. Chan, “CMOS-Compatible Time-of- Flight 3D Imaging Sensors and Systems,” in 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, IEEE, 2021, pp. 1–4.
[3] S. Lin, J. Liu, and M. D. Wong, “GAMER: GPU Accelerated Maze Routing,” in 2021 IEEE/ACM Inter- national Conference On Computer Aided Design (ICCAD), 2021, pp. 1–8.
[2] C. Chen, C. Tao, and N. Wong, “LiteGT: Efficient and Lightweight Graph Transformers,” in Proceedings of the 30th ACM International Conference on Information & Knowledge Management, ser. CIKM ’21, Virtual Event, Queensland, Australia: Association for Computing Machinery, 2021, pp. 161–170.
[1] C. Zhang, J. Xia, B. Yang, et al., “Citadel: Protecting Data Privacy and Model Confidentiality for Collaborative Learning,” in Proceedings of the ACM Symposium on Cloud Computing, ser. SoCC ’21, Seattle, WA, USA: Association for Computing Machinery, 2021, pp. 546–561.