RP1 addresses memory and data bandwidth problems to alleviate the bottlenecks of AI hardware by exploring integration of silicon-compatible emerging technologies with scaled silicon chips.
ReRAM-Based Circuits for Neuromorphic Computing
Project RP1-1 covers the development of 3D integrated chips, including both resistive random-access memory ReRAM and silicon CMOS based processors, for energy-efficient implementation of vector-by-matrix multiplication operations. RP1-1’s goal also includes investigation of suitability and the best use of high-density nonvolatile memory ReRAM for AI chips/systems in different target segments, through exploration of the tradeoffs among speed, density, footprint, energy consumption, variation and robustness.
3D Technology for AI Chips with High Connectivity
Project RP1-2 addresses the need to have massive amount of interconnects for connecting the huge number of computing and memory elements in neuromorphic computing. The current mainstream approach of off-chip memory has become the major bottleneck in speed and power/energy consumption due to resistance and capacitance. 3-D integration technologies – including 2.5D/3D and monolithic integration technologies – can address the interconnect problem providing an extra dimension in the physical space to connect different circuit elements. The approach offers the advantages of higher bandwidth and lower latency, resulting in more than 1,000x lower energy-delay product for the system, and smaller form factor of a chip and more tightly coupled circuit blocks.
High-Performance Silicon Photonic Technologies for AI System
Traditional computing systems are based on CMOS technologies and the ending of Moore’s Law is dramatically increasing the cost and energy consumption of growing computation capability demanded by AI applications. Silicon photonics advances promise great energy efficiency, ultra-high speed, and low latency compared to CMOS. Silicon photonics technologies open new opportunities for AI architectures, circuits, and tools to fully explore new approaches and address the challenges of post-Moore's Law AI systems.
Device Modeling from Technology to Neuromorphic Computing
Compact model plays a significant role in bridging emerging devices to applications. The traditional quasi-static based device modeling approach available in EDA tools is incapable of handling the dynamic memory device and neuromorphic computer systems which works with spikes. Project RP1-4 addresses a dynamic state varying modeling approach to solve the issue of memory simulation in EDA tools. The developed compact model will be able to provide detail simulation in the time domain in addition to the current-voltage domain.