RP3 - AI-Assisted EDA (Electronic Design Automation) for AI Hardware

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RP3 hopes to develop new design methodologies and design automation tools for AI chips.

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Design Methodology and EDA Tools for HW-SW Co-design of Deep Neural Networks and AI Algorithms

RP3-1:

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Figure RP3-1: Overall design flow and building modules for a framework co-designing DNN and hardware accelerator
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Project RP3-1 will develop methods and tools enabling hardware-software co-design with the objective of designing high-quality machine learning algorithms while taking hardware constraints and features on FPGA, GPU and accelerator into account, as well as enabling system design exploration and simulation efficiently for co-optimization of AI system software and hardware architectures under cost constraints.

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Physical Synthesis of AI Accelerators

RP3-2:

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Figure RP3-2: (a) Output of manual design for a very simple neural network with known optimal solution; (b) Output of a commercial EDA tool for the same neural network
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In Project RP3-2, leveraging our previous research and expertise on physical synthesis, we will focus on new solutions for physical synthesis of AI accelerators for which particular regularity or wire patterns in AI accelerators will be analyzed and taken into account. We will first investigate a high-performance yet efficient data-path extraction tool to identify critical structural path, and then feed the extracted data-path into our customized physical synthesis engine to automatically general AI chip layout.

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AI Enhanced Electronic Design Automation (AIEDA)

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Figure RP3-3: Example of AI enhanced design technology - Neural-ILT
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Today, with so much advancement in AI software and hardware, EDA has a great opportunity to be tremendously enhanced in both performance and computing efficiency. In this project, we will study fundamental problems in EDA with the objective of dramatically enhancing the efficiency and quality of EDA tools in order to make fast and high-quality AI chip design possible. Research in this aspect will lead us in taming the huge design complexity and shortening of the design cycle to meet better the time-to-market requirements, enabling the design of large-scale on-chip artificial neural networks with good performance and efficiency, which is an essential and winning factor for AI hardware design and manufacturing.