“Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System,” in 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023, pp. 1–5.

“GLARE: Accelerating Sparse DNN Inference Kernels with Global Memory Access Reduction,” in 2023 IEEE High Performance Extreme Computing Conference (HPEC), 2023.

 “A 10.8-14.5GHz 8-Phase 12.5%-Duty-Cycle Non-Overlapping LO Generator with Automatic Phase-and-Duty-Cycle Calibration for 60-GHz 8-Path-Filtering Sub- Sampling Receivers,” in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023, pp. 205–208.

 “Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, pp. 1–2.

“PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.

 “PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.

 “MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.

 “Lay-Net: Grafting Netlist Knowledge on Layout- Based Congestion Prediction,” in 2023 IEEE/ACM International Conference On Computer Aided De- sign (ICCAD), 2023.

“Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.

“Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.

“Algorithm/Hardware Co-design for Few-Shot Learning at the Edge,” in 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Invited paper, 2023.

“Accelerating Large Kernel Convolutions with Nested Winograd Transformation,” in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC), 2023.

 “A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication,” in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC), 2023, p. 6.

“Gain Cell Memory on Logic Platform - Device Guidelines for Oxide Semiconductor Transistor Materials Development,” in 2023 International Electron Devices Meeting (IEDM), 2023.

“Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-Objective Trust-Region Bayesian Optimization,” ACM Trans. Des. Autom. Electron. Syst., vol. 28, no. 5, Sep. 2023.

 “Overflow-Free Compute Memories for Edge AI Acceleration,” ACM Trans. Embed. Comput. Syst., vol. 22, no. 5s, Sep. 2023.

“Highly Trustworthy In-Sensor Cryptography for Image Encryption and Authentication,” ACS Nano, vol. 17, no. 11, pp. 10 291–10 299, 2023.

“EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry,” in ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, pp. 469–472.

“BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare,” in ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, pp. 225–228.

“MMExit: Enabling Fast and Efficient Multi-modal DNN Inference with Adaptive Network Exits,” in Euro-Par 2023: Parallel Processing, Cham: Springer Nature Switzerland, 2023, pp. 426–440.