Sections

Lead / Senior / Research Engineer

Ref. No.: AC0007

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Job Description

The AI Chip Centre for Emerging Smart Systems (ACCESS) is a multi-disciplinary center for advancing IC design and design automation technologies to enable novel data-centric computing paradigms supporting a wide range of AI applications. The research agenda in ACCESS is organized into four research programs, addressing four key technical areas, including 1) Enabling Technology for Emerging Computer Systems, 2) Architecture and Heterogeneous System Integration, 3) AI-Assisted EDA for AI Hardware, and 4) Hardware-Accelerated AI Applications.

Responsibilities 

The Research Engineers (including Lead Research Engineers, Senior Research Engineers, and Research Engineers) are expected to be involved in the development of one or multiple research programs and projects in the Center. They will conduct research and development tasks that are assigned by the supervisor and are required to station and work at the Hong Kong Science Park, with occasional business travels to HKUST Clear Water Bay Campus and other Partner Universities of the Center when needed.

Requirements 

Applicants should have a Master degree (MSc or MPhil) or above preferably in electronics, electrical or computer engineering, computer science, or relevant, and at least 2 years of post-qualification experience in R&D or equivalent. In-depth knowledge and experience in integrated circuit design, design automation or broadly microelectronics are essential. Specifically, R&D as well as hand-on implementation experiences in the following area(s) with relevance to the design of AI accelerators are preferred (but not limited to):

  • ASIC design, FPGA prototyping, AI algorithm design;
  • Solid knowledge and experience in at least one of the following areas: digital circuit architecture design and implementation, common analog circuit design, processor simulation/compilation algorithms or design automation algorithms;
  • Strong programming skills of at least one of the following languages: Verilog/VHDL, Verilog-A, System Verilog, Python, C/C++, and HLS;
  • R&D experiences using Cadence and Synopsys EDA tools, machine learning frameworks (such as Caffe, Tensorflow, PyTorch, etc.), or architecture simulation/compilation toolchain (such as GEM5, TVM, Glow, etc.).

The ideal candidate should have strong R&D motivation and sense of responsibility, ability to multi-task and work independently, and a good command of written and spoken English.

Terms of Appointment

Starting salary will be commensurate with qualifications and experience. Fringe benefits including annual leave, medical and dental benefits will be provided.

ACCESS is an equal opportunity employer and welcomes applications from all qualified candidates.

Application Procedure

For applications/nominations together with a full curriculum vitae indicating their current and expected salaries, please send it to Ms Phoebe CHEUNG (hraccess@ust.hk). Review of applications will begin shortly and continue until the positions are filled. Only shortlisted candidates will be notified. *Please mark “PRIVATE & CONFIDENTIAL” and quote the position applied for and its reference number in the subject of the email.

(Information provided by applications will be used for recruitment and other employment-related purposes.)

 

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